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<BR><PRE><A name="Report Header"></A>
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.2.446
Mon Apr 06 16:34:58 2020

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design file:     top
Device,speed:    LCMXO2-7000HE,M
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------



</A><A name="FREQUENCY NET 'osc_clk' 88.670000 MH"></A>================================================================================
Preference: FREQUENCY NET "osc_clk" 88.670000 MHz ;
            10 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
<font color=#000000> 

Passed: The following path meets requirements by 0.303ns
 </font>
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:CIC1Sin/SLICE_2186">CIC1Sin/v_comb_66</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    FF         Data in        <A href="#@comp:CIC1Sin/SLICE_2220">CIC1Sin/d_out_i0_i7</A>  (to <A href="#@net:osc_clk">osc_clk</A> +)
                   FF                        <A href="#@net:CIC1Sin/d_out_i0_i6">CIC1Sin/d_out_i0_i6</A>

   Delay:               0.279ns  (47.7% logic, 52.3% route), 1 logic levels.

 Constraint Details:

      0.279ns physical path delay CIC1Sin/SLICE_2186 to CIC1Sin/SLICE_2220 meets
     -0.024ns CE_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.024ns) by 0.303ns

 Physical Path Details:

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:REG_DEL, 0.133,R9C23B.CLK,R9C23B.Q0,CIC1Sin/SLICE_2186:ROUTE, 0.146,R9C23B.Q0,R9C23D.CE,CIC1Sin/v_comb">Data path</A> CIC1Sin/SLICE_2186 to CIC1Sin/SLICE_2220:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C23B.CLK to      R9C23B.Q0 <A href="#@comp:CIC1Sin/SLICE_2186">CIC1Sin/SLICE_2186</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE        17     0.146<A href="#@net:CIC1Sin/v_comb:R9C23B.Q0:R9C23D.CE:0.146">      R9C23B.Q0 to R9C23D.CE     </A> <A href="#@net:CIC1Sin/v_comb">CIC1Sin/v_comb</A> (to <A href="#@net:osc_clk">osc_clk</A>)
                  --------
                    0.279   (47.7% logic, 52.3% route), 1 logic levels.

 Clock Skew Details: 

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.443,OSC.OSC,R9C23B.CLK,osc_clk">Source Clock Path</A> OSCH_inst to CIC1Sin/SLICE_2186:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.443<A href="#@net:osc_clk:OSC.OSC:R9C23B.CLK:1.443">        OSC.OSC to R9C23B.CLK    </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.443   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.443,OSC.OSC,R9C23D.CLK,osc_clk">Destination Clock Path</A> OSCH_inst to CIC1Sin/SLICE_2220:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.443<A href="#@net:osc_clk:OSC.OSC:R9C23D.CLK:1.443">        OSC.OSC to R9C23D.CLK    </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.443   (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000> 

Passed: The following path meets requirements by 0.304ns
 </font>
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:CIC1Cos/SLICE_1935">CIC1Cos/v_comb_66</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    FF         Data in        <A href="#@comp:SLICE_2192">CIC1Cos/d_out_i0_i9</A>  (to <A href="#@net:osc_clk">osc_clk</A> +)
                   FF                        <A href="#@net:CIC1Cos/d_out_i0_i8">CIC1Cos/d_out_i0_i8</A>

   Delay:               0.280ns  (47.5% logic, 52.5% route), 1 logic levels.

 Constraint Details:

      0.280ns physical path delay CIC1Cos/SLICE_1935 to SLICE_2192 meets
     -0.024ns CE_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.024ns) by 0.304ns

 Physical Path Details:

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:REG_DEL, 0.133,R9C25B.CLK,R9C25B.Q0,CIC1Cos/SLICE_1935:ROUTE, 0.147,R9C25B.Q0,R9C25D.CE,CIC1Cos/v_comb">Data path</A> CIC1Cos/SLICE_1935 to SLICE_2192:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C25B.CLK to      R9C25B.Q0 <A href="#@comp:CIC1Cos/SLICE_1935">CIC1Cos/SLICE_1935</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE        15     0.147<A href="#@net:CIC1Cos/v_comb:R9C25B.Q0:R9C25D.CE:0.147">      R9C25B.Q0 to R9C25D.CE     </A> <A href="#@net:CIC1Cos/v_comb">CIC1Cos/v_comb</A> (to <A href="#@net:osc_clk">osc_clk</A>)
                  --------
                    0.280   (47.5% logic, 52.5% route), 1 logic levels.

 Clock Skew Details: 

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.443,OSC.OSC,R9C25B.CLK,osc_clk">Source Clock Path</A> OSCH_inst to CIC1Cos/SLICE_1935:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.443<A href="#@net:osc_clk:OSC.OSC:R9C25B.CLK:1.443">        OSC.OSC to R9C25B.CLK    </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.443   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.443,OSC.OSC,R9C25D.CLK,osc_clk">Destination Clock Path</A> OSCH_inst to SLICE_2192:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.443<A href="#@net:osc_clk:OSC.OSC:R9C25D.CLK:1.443">        OSC.OSC to R9C25D.CLK    </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.443   (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000> 

Passed: The following path meets requirements by 0.306ns
 </font>
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:Mixer1/SLICE_2225">Mixer1/RFInR1_13</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    FF         Data in        <A href="#@comp:Mixer1/SLICE_2225">Mixer1/RFInR_14</A>  (to <A href="#@net:osc_clk">osc_clk</A> +)

   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.

 Constraint Details:

      0.287ns physical path delay Mixer1/SLICE_2225 to Mixer1/SLICE_2225 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.306ns

 Physical Path Details:

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:REG_DEL, 0.133,R2C19A.CLK,R2C19A.Q1,Mixer1/SLICE_2225:ROUTE, 0.154,R2C19A.Q1,R2C19A.M0,DiffOut_c">Data path</A> Mixer1/SLICE_2225 to Mixer1/SLICE_2225:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C19A.CLK to      R2C19A.Q1 <A href="#@comp:Mixer1/SLICE_2225">Mixer1/SLICE_2225</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         2     0.154<A href="#@net:DiffOut_c:R2C19A.Q1:R2C19A.M0:0.154">      R2C19A.Q1 to R2C19A.M0     </A> <A href="#@net:DiffOut_c">DiffOut_c</A> (to <A href="#@net:osc_clk">osc_clk</A>)
                  --------
                    0.287   (46.3% logic, 53.7% route), 1 logic levels.

 Clock Skew Details: 

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.443,OSC.OSC,R2C19A.CLK,osc_clk">Source Clock Path</A> OSCH_inst to Mixer1/SLICE_2225:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.443<A href="#@net:osc_clk:OSC.OSC:R2C19A.CLK:1.443">        OSC.OSC to R2C19A.CLK    </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.443   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.443,OSC.OSC,R2C19A.CLK,osc_clk">Destination Clock Path</A> OSCH_inst to Mixer1/SLICE_2225:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.443<A href="#@net:osc_clk:OSC.OSC:R2C19A.CLK:1.443">        OSC.OSC to R2C19A.CLK    </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.443   (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000> 

Passed: The following path meets requirements by 0.306ns
 </font>
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:CIC1Cos/SLICE_1588">CIC1Cos/d6_i0_i33</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    FF         Data in        <A href="#@comp:CIC1Cos/SLICE_1724">CIC1Cos/d_d6_i0_i33</A>  (to <A href="#@net:osc_clk">osc_clk</A> +)

   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.

 Constraint Details:

      0.287ns physical path delay CIC1Cos/SLICE_1588 to CIC1Cos/SLICE_1724 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.306ns

 Physical Path Details:

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:REG_DEL, 0.133,R22C39B.CLK,R22C39B.Q0,CIC1Cos/SLICE_1588:ROUTE, 0.154,R22C39B.Q0,R22C39D.M0,CIC1Cos/d6_33">Data path</A> CIC1Cos/SLICE_1588 to CIC1Cos/SLICE_1724:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R22C39B.CLK to     R22C39B.Q0 <A href="#@comp:CIC1Cos/SLICE_1588">CIC1Cos/SLICE_1588</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         2     0.154<A href="#@net:CIC1Cos/d6_33:R22C39B.Q0:R22C39D.M0:0.154">     R22C39B.Q0 to R22C39D.M0    </A> <A href="#@net:CIC1Cos/d6_33">CIC1Cos/d6_33</A> (to <A href="#@net:osc_clk">osc_clk</A>)
                  --------
                    0.287   (46.3% logic, 53.7% route), 1 logic levels.

 Clock Skew Details: 

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.425,OSC.OSC,R22C39B.CLK,osc_clk">Source Clock Path</A> OSCH_inst to CIC1Cos/SLICE_1588:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.425<A href="#@net:osc_clk:OSC.OSC:R22C39B.CLK:1.425">        OSC.OSC to R22C39B.CLK   </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.425,OSC.OSC,R22C39D.CLK,osc_clk">Destination Clock Path</A> OSCH_inst to CIC1Cos/SLICE_1724:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.425<A href="#@net:osc_clk:OSC.OSC:R22C39D.CLK:1.425">        OSC.OSC to R22C39D.CLK   </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000> 

Passed: The following path meets requirements by 0.306ns
 </font>
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:CIC1Cos/SLICE_1588">CIC1Cos/d6_i0_i34</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    FF         Data in        <A href="#@comp:CIC1Cos/SLICE_1724">CIC1Cos/d_d6_i0_i34</A>  (to <A href="#@net:osc_clk">osc_clk</A> +)

   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.

 Constraint Details:

      0.287ns physical path delay CIC1Cos/SLICE_1588 to CIC1Cos/SLICE_1724 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.306ns

 Physical Path Details:

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:REG_DEL, 0.133,R22C39B.CLK,R22C39B.Q1,CIC1Cos/SLICE_1588:ROUTE, 0.154,R22C39B.Q1,R22C39D.M1,CIC1Cos/d6_34">Data path</A> CIC1Cos/SLICE_1588 to CIC1Cos/SLICE_1724:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R22C39B.CLK to     R22C39B.Q1 <A href="#@comp:CIC1Cos/SLICE_1588">CIC1Cos/SLICE_1588</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         2     0.154<A href="#@net:CIC1Cos/d6_34:R22C39B.Q1:R22C39D.M1:0.154">     R22C39B.Q1 to R22C39D.M1    </A> <A href="#@net:CIC1Cos/d6_34">CIC1Cos/d6_34</A> (to <A href="#@net:osc_clk">osc_clk</A>)
                  --------
                    0.287   (46.3% logic, 53.7% route), 1 logic levels.

 Clock Skew Details: 

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.425,OSC.OSC,R22C39B.CLK,osc_clk">Source Clock Path</A> OSCH_inst to CIC1Cos/SLICE_1588:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.425<A href="#@net:osc_clk:OSC.OSC:R22C39B.CLK:1.425">        OSC.OSC to R22C39B.CLK   </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.425,OSC.OSC,R22C39D.CLK,osc_clk">Destination Clock Path</A> OSCH_inst to CIC1Cos/SLICE_1724:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.425<A href="#@net:osc_clk:OSC.OSC:R22C39D.CLK:1.425">        OSC.OSC to R22C39D.CLK   </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000> 

Passed: The following path meets requirements by 0.306ns
 </font>
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:CIC1Cos/SLICE_1893">CIC1Cos/d_tmp_i0_i2</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    FF         Data in        <A href="#@comp:CIC1Cos/SLICE_1856">CIC1Cos/d_d_tmp_i0_i2</A>  (to <A href="#@net:osc_clk">osc_clk</A> +)

   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.

 Constraint Details:

      0.287ns physical path delay CIC1Cos/SLICE_1893 to CIC1Cos/SLICE_1856 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.306ns

 Physical Path Details:

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:REG_DEL, 0.133,R23C35A.CLK,R23C35A.Q0,CIC1Cos/SLICE_1893:ROUTE, 0.154,R23C35A.Q0,R23C35D.M0,CIC1Cos/d_tmp_2">Data path</A> CIC1Cos/SLICE_1893 to CIC1Cos/SLICE_1856:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R23C35A.CLK to     R23C35A.Q0 <A href="#@comp:CIC1Cos/SLICE_1893">CIC1Cos/SLICE_1893</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         2     0.154<A href="#@net:CIC1Cos/d_tmp_2:R23C35A.Q0:R23C35D.M0:0.154">     R23C35A.Q0 to R23C35D.M0    </A> <A href="#@net:CIC1Cos/d_tmp_2">CIC1Cos/d_tmp_2</A> (to <A href="#@net:osc_clk">osc_clk</A>)
                  --------
                    0.287   (46.3% logic, 53.7% route), 1 logic levels.

 Clock Skew Details: 

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.425,OSC.OSC,R23C35A.CLK,osc_clk">Source Clock Path</A> OSCH_inst to CIC1Cos/SLICE_1893:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.425<A href="#@net:osc_clk:OSC.OSC:R23C35A.CLK:1.425">        OSC.OSC to R23C35A.CLK   </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.425,OSC.OSC,R23C35D.CLK,osc_clk">Destination Clock Path</A> OSCH_inst to CIC1Cos/SLICE_1856:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.425<A href="#@net:osc_clk:OSC.OSC:R23C35D.CLK:1.425">        OSC.OSC to R23C35D.CLK   </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000> 

Passed: The following path meets requirements by 0.306ns
 </font>
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:CIC1Cos/SLICE_1893">CIC1Cos/d_tmp_i0_i3</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    FF         Data in        <A href="#@comp:CIC1Cos/SLICE_1856">CIC1Cos/d_d_tmp_i0_i3</A>  (to <A href="#@net:osc_clk">osc_clk</A> +)

   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.

 Constraint Details:

      0.287ns physical path delay CIC1Cos/SLICE_1893 to CIC1Cos/SLICE_1856 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.306ns

 Physical Path Details:

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:REG_DEL, 0.133,R23C35A.CLK,R23C35A.Q1,CIC1Cos/SLICE_1893:ROUTE, 0.154,R23C35A.Q1,R23C35D.M1,CIC1Cos/d_tmp_3">Data path</A> CIC1Cos/SLICE_1893 to CIC1Cos/SLICE_1856:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R23C35A.CLK to     R23C35A.Q1 <A href="#@comp:CIC1Cos/SLICE_1893">CIC1Cos/SLICE_1893</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         2     0.154<A href="#@net:CIC1Cos/d_tmp_3:R23C35A.Q1:R23C35D.M1:0.154">     R23C35A.Q1 to R23C35D.M1    </A> <A href="#@net:CIC1Cos/d_tmp_3">CIC1Cos/d_tmp_3</A> (to <A href="#@net:osc_clk">osc_clk</A>)
                  --------
                    0.287   (46.3% logic, 53.7% route), 1 logic levels.

 Clock Skew Details: 

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.425,OSC.OSC,R23C35A.CLK,osc_clk">Source Clock Path</A> OSCH_inst to CIC1Cos/SLICE_1893:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.425<A href="#@net:osc_clk:OSC.OSC:R23C35A.CLK:1.425">        OSC.OSC to R23C35A.CLK   </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.425,OSC.OSC,R23C35D.CLK,osc_clk">Destination Clock Path</A> OSCH_inst to CIC1Cos/SLICE_1856:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.425<A href="#@net:osc_clk:OSC.OSC:R23C35D.CLK:1.425">        OSC.OSC to R23C35D.CLK   </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000> 

Passed: The following path meets requirements by 0.307ns
 </font>
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:CIC1Cos/SLICE_1108">CIC1Cos/d5_i67</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    FF         Data in        <A href="#@comp:CIC1Cos/SLICE_1925">CIC1Cos/d_tmp_i0_i67</A>  (to <A href="#@net:osc_clk">osc_clk</A> +)

   Delay:               0.288ns  (46.2% logic, 53.8% route), 1 logic levels.

 Constraint Details:

      0.288ns physical path delay CIC1Cos/SLICE_1108 to CIC1Cos/SLICE_1925 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.307ns

 Physical Path Details:

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:REG_DEL, 0.133,R15C31A.CLK,R15C31A.Q1,CIC1Cos/SLICE_1108:ROUTE, 0.155,R15C31A.Q1,R15C31D.M1,CIC1Cos/d5_67">Data path</A> CIC1Cos/SLICE_1108 to CIC1Cos/SLICE_1925:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R15C31A.CLK to     R15C31A.Q1 <A href="#@comp:CIC1Cos/SLICE_1108">CIC1Cos/SLICE_1108</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         3     0.155<A href="#@net:CIC1Cos/d5_67:R15C31A.Q1:R15C31D.M1:0.155">     R15C31A.Q1 to R15C31D.M1    </A> <A href="#@net:CIC1Cos/d5_67">CIC1Cos/d5_67</A> (to <A href="#@net:osc_clk">osc_clk</A>)
                  --------
                    0.288   (46.2% logic, 53.8% route), 1 logic levels.

 Clock Skew Details: 

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.443,OSC.OSC,R15C31A.CLK,osc_clk">Source Clock Path</A> OSCH_inst to CIC1Cos/SLICE_1108:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.443<A href="#@net:osc_clk:OSC.OSC:R15C31A.CLK:1.443">        OSC.OSC to R15C31A.CLK   </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.443   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.443,OSC.OSC,R15C31D.CLK,osc_clk">Destination Clock Path</A> OSCH_inst to CIC1Cos/SLICE_1925:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.443<A href="#@net:osc_clk:OSC.OSC:R15C31D.CLK:1.443">        OSC.OSC to R15C31D.CLK   </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.443   (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000> 

Passed: The following path meets requirements by 0.307ns
 </font>
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:SinCos1/SLICE_2275">SinCos1/FF_55</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    FF         Data in        <A href="#@comp:SinCos1/SLICE_2275">SinCos1/FF_27</A>  (to <A href="#@net:osc_clk">osc_clk</A> +)

   Delay:               0.288ns  (46.2% logic, 53.8% route), 1 logic levels.

 Constraint Details:

      0.288ns physical path delay SinCos1/SLICE_2275 to SinCos1/SLICE_2275 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.307ns

 Physical Path Details:

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:REG_DEL, 0.133,R9C4B.CLK,R9C4B.Q1,SinCos1/SLICE_2275:ROUTE, 0.155,R9C4B.Q1,R9C4B.M0,SinCos1/mx_ctrl_r_1">Data path</A> SinCos1/SLICE_2275 to SinCos1/SLICE_2275:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R9C4B.CLK to       R9C4B.Q1 <A href="#@comp:SinCos1/SLICE_2275">SinCos1/SLICE_2275</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         3     0.155<A href="#@net:SinCos1/mx_ctrl_r_1:R9C4B.Q1:R9C4B.M0:0.155">       R9C4B.Q1 to R9C4B.M0      </A> <A href="#@net:SinCos1/mx_ctrl_r_1">SinCos1/mx_ctrl_r_1</A> (to <A href="#@net:osc_clk">osc_clk</A>)
                  --------
                    0.288   (46.2% logic, 53.8% route), 1 logic levels.

 Clock Skew Details: 

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.443,OSC.OSC,R9C4B.CLK,osc_clk">Source Clock Path</A> OSCH_inst to SinCos1/SLICE_2275:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.443<A href="#@net:osc_clk:OSC.OSC:R9C4B.CLK:1.443">        OSC.OSC to R9C4B.CLK     </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.443   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.443,OSC.OSC,R9C4B.CLK,osc_clk">Destination Clock Path</A> OSCH_inst to SinCos1/SLICE_2275:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.443<A href="#@net:osc_clk:OSC.OSC:R9C4B.CLK:1.443">        OSC.OSC to R9C4B.CLK     </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.443   (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000> 

Passed: The following path meets requirements by 0.307ns
 </font>
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:CIC1Cos/SLICE_1108">CIC1Cos/d5_i66</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    FF         Data in        <A href="#@comp:CIC1Cos/SLICE_1925">CIC1Cos/d_tmp_i0_i66</A>  (to <A href="#@net:osc_clk">osc_clk</A> +)

   Delay:               0.288ns  (46.2% logic, 53.8% route), 1 logic levels.

 Constraint Details:

      0.288ns physical path delay CIC1Cos/SLICE_1108 to CIC1Cos/SLICE_1925 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.307ns

 Physical Path Details:

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:REG_DEL, 0.133,R15C31A.CLK,R15C31A.Q0,CIC1Cos/SLICE_1108:ROUTE, 0.155,R15C31A.Q0,R15C31D.M0,CIC1Cos/d5_66">Data path</A> CIC1Cos/SLICE_1108 to CIC1Cos/SLICE_1925:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R15C31A.CLK to     R15C31A.Q0 <A href="#@comp:CIC1Cos/SLICE_1108">CIC1Cos/SLICE_1108</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         3     0.155<A href="#@net:CIC1Cos/d5_66:R15C31A.Q0:R15C31D.M0:0.155">     R15C31A.Q0 to R15C31D.M0    </A> <A href="#@net:CIC1Cos/d5_66">CIC1Cos/d5_66</A> (to <A href="#@net:osc_clk">osc_clk</A>)
                  --------
                    0.288   (46.2% logic, 53.8% route), 1 logic levels.

 Clock Skew Details: 

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.443,OSC.OSC,R15C31A.CLK,osc_clk">Source Clock Path</A> OSCH_inst to CIC1Cos/SLICE_1108:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.443<A href="#@net:osc_clk:OSC.OSC:R15C31A.CLK:1.443">        OSC.OSC to R15C31A.CLK   </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.443   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:FREQUENCY NET 'osc_clk' 88.670000 MHz ;:ROUTE, 1.443,OSC.OSC,R15C31D.CLK,osc_clk">Destination Clock Path</A> OSCH_inst to CIC1Cos/SLICE_1925:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.443<A href="#@net:osc_clk:OSC.OSC:R15C31D.CLK:1.443">        OSC.OSC to R15C31D.CLK   </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.443   (0.0% logic, 100.0% route), 0 logic levels.


</A><A name="CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk"></A>================================================================================
Preference: CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET "osc_clk" ;
            10 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 2.857ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:Mixer1/SLICE_2225">Mixer1/RFInR1_13</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    Port       Pad            <A href="#@comp:DiffOut">DiffOut</A>

   Data Path Delay:     1.666ns  (73.0% logic, 27.0% route), 2 logic levels.

   Clock Path Delay:    1.191ns  (0.0% logic, 100.0% route), 0 logic levels.

 Constraint Details:
      1.191ns delay OSCH_inst to Mixer1/SLICE_2225 and
      1.666ns delay Mixer1/SLICE_2225 to DiffOut (totaling 2.857ns) meets
      0.000ns hold offset OSCH_inst to DiffOut by 2.857ns

 Physical Path Details:

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:ROUTE, 1.191,OSC.OSC,R2C19A.CLK,osc_clk">Clock path</A> OSCH_inst to Mixer1/SLICE_2225:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.191<A href="#@net:osc_clk:OSC.OSC:R2C19A.CLK:1.191">        OSC.OSC to R2C19A.CLK    </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.191   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:REG_DEL, 0.133,R2C19A.CLK,R2C19A.Q1,Mixer1/SLICE_2225:ROUTE, 0.449,R2C19A.Q1,122.PADDO,DiffOut_c:DOPAD_DEL, 1.084,122.PADDO,122.PAD,DiffOut">Data path</A> Mixer1/SLICE_2225 to DiffOut:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C19A.CLK to      R2C19A.Q1 <A href="#@comp:Mixer1/SLICE_2225">Mixer1/SLICE_2225</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         2     0.449<A href="#@net:DiffOut_c:R2C19A.Q1:122.PADDO:0.449">      R2C19A.Q1 to 122.PADDO     </A> <A href="#@net:DiffOut_c">DiffOut_c</A>
DOPAD_DEL   ---     1.084      122.PADDO to        122.PAD <A href="#@comp:DiffOut">DiffOut</A>
                  --------
                    1.666   (73.0% logic, 27.0% route), 2 logic levels.


Passed:  The following path meets requirements by 2.875ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:CIC1Sin/SLICE_2220">CIC1Sin/d_out_i0_i6</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    Port       Pad            <A href="#@comp:MYLED[0]">MYLED[0]</A>

   Data Path Delay:     1.684ns  (64.5% logic, 35.5% route), 2 logic levels.

   Clock Path Delay:    1.191ns  (0.0% logic, 100.0% route), 0 logic levels.

 Constraint Details:
      1.191ns delay OSCH_inst to CIC1Sin/SLICE_2220 and
      1.684ns delay CIC1Sin/SLICE_2220 to MYLED[0] (totaling 2.875ns) meets
      0.000ns hold offset OSCH_inst to MYLED[0] by 2.875ns

 Physical Path Details:

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:ROUTE, 1.191,OSC.OSC,R9C23D.CLK,osc_clk">Clock path</A> OSCH_inst to CIC1Sin/SLICE_2220:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.191<A href="#@net:osc_clk:OSC.OSC:R9C23D.CLK:1.191">        OSC.OSC to R9C23D.CLK    </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.191   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:REG_DEL, 0.133,R9C23D.CLK,R9C23D.Q0,CIC1Sin/SLICE_2220:ROUTE, 0.598,R9C23D.Q0,97.PADDO,MYLED_c_0:DOPAD_DEL, 0.953,97.PADDO,97.PAD,MYLED[0]">Data path</A> CIC1Sin/SLICE_2220 to MYLED[0]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C23D.CLK to      R9C23D.Q0 <A href="#@comp:CIC1Sin/SLICE_2220">CIC1Sin/SLICE_2220</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         2     0.598<A href="#@net:MYLED_c_0:R9C23D.Q0:97.PADDO:0.598">      R9C23D.Q0 to 97.PADDO      </A> <A href="#@net:MYLED_c_0">MYLED_c_0</A>
DOPAD_DEL   ---     0.953       97.PADDO to         97.PAD <A href="#@comp:MYLED[0]">MYLED[0]</A>
                  --------
                    1.684   (64.5% logic, 35.5% route), 2 logic levels.


Passed:  The following path meets requirements by 3.016ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:CIC1Sin/SLICE_2223">CIC1Sin/d_out_i0_i11</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    Port       Pad            <A href="#@comp:MYLED[5]">MYLED[5]</A>

   Data Path Delay:     1.825ns  (59.5% logic, 40.5% route), 2 logic levels.

   Clock Path Delay:    1.191ns  (0.0% logic, 100.0% route), 0 logic levels.

 Constraint Details:
      1.191ns delay OSCH_inst to CIC1Sin/SLICE_2223 and
      1.825ns delay CIC1Sin/SLICE_2223 to MYLED[5] (totaling 3.016ns) meets
      0.000ns hold offset OSCH_inst to MYLED[5] by 3.016ns

 Physical Path Details:

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:ROUTE, 1.191,OSC.OSC,R9C22D.CLK,osc_clk">Clock path</A> OSCH_inst to CIC1Sin/SLICE_2223:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.191<A href="#@net:osc_clk:OSC.OSC:R9C22D.CLK:1.191">        OSC.OSC to R9C22D.CLK    </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.191   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:REG_DEL, 0.133,R9C22D.CLK,R9C22D.Q0,CIC1Sin/SLICE_2223:ROUTE, 0.739,R9C22D.Q0,105.PADDO,MYLED_c_5:DOPAD_DEL, 0.953,105.PADDO,105.PAD,MYLED[5]">Data path</A> CIC1Sin/SLICE_2223 to MYLED[5]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C22D.CLK to      R9C22D.Q0 <A href="#@comp:CIC1Sin/SLICE_2223">CIC1Sin/SLICE_2223</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         2     0.739<A href="#@net:MYLED_c_5:R9C22D.Q0:105.PADDO:0.739">      R9C22D.Q0 to 105.PADDO     </A> <A href="#@net:MYLED_c_5">MYLED_c_5</A>
DOPAD_DEL   ---     0.953      105.PADDO to        105.PAD <A href="#@comp:MYLED[5]">MYLED[5]</A>
                  --------
                    1.825   (59.5% logic, 40.5% route), 2 logic levels.


Passed:  The following path meets requirements by 3.158ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:CIC1Sin/SLICE_2220">CIC1Sin/d_out_i0_i7</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    Port       Pad            <A href="#@comp:MYLED[1]">MYLED[1]</A>

   Data Path Delay:     1.967ns  (55.2% logic, 44.8% route), 2 logic levels.

   Clock Path Delay:    1.191ns  (0.0% logic, 100.0% route), 0 logic levels.

 Constraint Details:
      1.191ns delay OSCH_inst to CIC1Sin/SLICE_2220 and
      1.967ns delay CIC1Sin/SLICE_2220 to MYLED[1] (totaling 3.158ns) meets
      0.000ns hold offset OSCH_inst to MYLED[1] by 3.158ns

 Physical Path Details:

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:ROUTE, 1.191,OSC.OSC,R9C23D.CLK,osc_clk">Clock path</A> OSCH_inst to CIC1Sin/SLICE_2220:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.191<A href="#@net:osc_clk:OSC.OSC:R9C23D.CLK:1.191">        OSC.OSC to R9C23D.CLK    </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.191   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:REG_DEL, 0.133,R9C23D.CLK,R9C23D.Q1,CIC1Sin/SLICE_2220:ROUTE, 0.881,R9C23D.Q1,98.PADDO,MYLED_c_1:DOPAD_DEL, 0.953,98.PADDO,98.PAD,MYLED[1]">Data path</A> CIC1Sin/SLICE_2220 to MYLED[1]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C23D.CLK to      R9C23D.Q1 <A href="#@comp:CIC1Sin/SLICE_2220">CIC1Sin/SLICE_2220</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         2     0.881<A href="#@net:MYLED_c_1:R9C23D.Q1:98.PADDO:0.881">      R9C23D.Q1 to 98.PADDO      </A> <A href="#@net:MYLED_c_1">MYLED_c_1</A>
DOPAD_DEL   ---     0.953       98.PADDO to         98.PAD <A href="#@comp:MYLED[1]">MYLED[1]</A>
                  --------
                    1.967   (55.2% logic, 44.8% route), 2 logic levels.


Passed:  The following path meets requirements by 3.261ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:CIC1Sin/SLICE_2221">CIC1Sin/d_out_i0_i9</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    Port       Pad            <A href="#@comp:MYLED[3]">MYLED[3]</A>

   Data Path Delay:     2.070ns  (52.5% logic, 47.5% route), 2 logic levels.

   Clock Path Delay:    1.191ns  (0.0% logic, 100.0% route), 0 logic levels.

 Constraint Details:
      1.191ns delay OSCH_inst to CIC1Sin/SLICE_2221 and
      2.070ns delay CIC1Sin/SLICE_2221 to MYLED[3] (totaling 3.261ns) meets
      0.000ns hold offset OSCH_inst to MYLED[3] by 3.261ns

 Physical Path Details:

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:ROUTE, 1.191,OSC.OSC,R9C22B.CLK,osc_clk">Clock path</A> OSCH_inst to CIC1Sin/SLICE_2221:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.191<A href="#@net:osc_clk:OSC.OSC:R9C22B.CLK:1.191">        OSC.OSC to R9C22B.CLK    </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.191   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:REG_DEL, 0.133,R9C22B.CLK,R9C22B.Q1,CIC1Sin/SLICE_2221:ROUTE, 0.984,R9C22B.Q1,100.PADDO,MYLED_c_3:DOPAD_DEL, 0.953,100.PADDO,100.PAD,MYLED[3]">Data path</A> CIC1Sin/SLICE_2221 to MYLED[3]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C22B.CLK to      R9C22B.Q1 <A href="#@comp:CIC1Sin/SLICE_2221">CIC1Sin/SLICE_2221</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         2     0.984<A href="#@net:MYLED_c_3:R9C22B.Q1:100.PADDO:0.984">      R9C22B.Q1 to 100.PADDO     </A> <A href="#@net:MYLED_c_3">MYLED_c_3</A>
DOPAD_DEL   ---     0.953      100.PADDO to        100.PAD <A href="#@comp:MYLED[3]">MYLED[3]</A>
                  --------
                    2.070   (52.5% logic, 47.5% route), 2 logic levels.


Passed:  The following path meets requirements by 3.289ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:CIC1Sin/SLICE_2221">CIC1Sin/d_out_i0_i8</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    Port       Pad            <A href="#@comp:MYLED[2]">MYLED[2]</A>

   Data Path Delay:     2.098ns  (51.8% logic, 48.2% route), 2 logic levels.

   Clock Path Delay:    1.191ns  (0.0% logic, 100.0% route), 0 logic levels.

 Constraint Details:
      1.191ns delay OSCH_inst to CIC1Sin/SLICE_2221 and
      2.098ns delay CIC1Sin/SLICE_2221 to MYLED[2] (totaling 3.289ns) meets
      0.000ns hold offset OSCH_inst to MYLED[2] by 3.289ns

 Physical Path Details:

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:ROUTE, 1.191,OSC.OSC,R9C22B.CLK,osc_clk">Clock path</A> OSCH_inst to CIC1Sin/SLICE_2221:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.191<A href="#@net:osc_clk:OSC.OSC:R9C22B.CLK:1.191">        OSC.OSC to R9C22B.CLK    </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.191   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:REG_DEL, 0.133,R9C22B.CLK,R9C22B.Q0,CIC1Sin/SLICE_2221:ROUTE, 1.012,R9C22B.Q0,99.PADDO,MYLED_c_2:DOPAD_DEL, 0.953,99.PADDO,99.PAD,MYLED[2]">Data path</A> CIC1Sin/SLICE_2221 to MYLED[2]:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C22B.CLK to      R9C22B.Q0 <A href="#@comp:CIC1Sin/SLICE_2221">CIC1Sin/SLICE_2221</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         2     1.012<A href="#@net:MYLED_c_2:R9C22B.Q0:99.PADDO:1.012">      R9C22B.Q0 to 99.PADDO      </A> <A href="#@net:MYLED_c_2">MYLED_c_2</A>
DOPAD_DEL   ---     0.953       99.PADDO to         99.PAD <A href="#@comp:MYLED[2]">MYLED[2]</A>
                  --------
                    2.098   (51.8% logic, 48.2% route), 2 logic levels.


Passed:  The following path meets requirements by 3.495ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:PWM1/SLICE_6">PWM1/PWMOut_15</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    Port       Pad            <A href="#@comp:PWMOutP3">PWMOutP3</A>

   Data Path Delay:     2.304ns  (52.8% logic, 47.2% route), 2 logic levels.

   Clock Path Delay:    1.191ns  (0.0% logic, 100.0% route), 0 logic levels.

 Constraint Details:
      1.191ns delay OSCH_inst to PWM1/SLICE_6 and
      2.304ns delay PWM1/SLICE_6 to PWMOutP3 (totaling 3.495ns) meets
      0.000ns hold offset OSCH_inst to PWMOutP3 by 3.495ns

 Physical Path Details:

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:ROUTE, 1.191,OSC.OSC,R12C25B.CLK,osc_clk">Clock path</A> OSCH_inst to PWM1/SLICE_6:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.191<A href="#@net:osc_clk:OSC.OSC:R12C25B.CLK:1.191">        OSC.OSC to R12C25B.CLK   </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.191   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:REG_DEL, 0.133,R12C25B.CLK,R12C25B.Q1,PWM1/SLICE_6:ROUTE, 1.087,R12C25B.Q1,68.PADDO,PWMOutP4_c:DOPAD_DEL, 1.084,68.PADDO,68.PAD,PWMOutP3">Data path</A> PWM1/SLICE_6 to PWMOutP3:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R12C25B.CLK to     R12C25B.Q1 <A href="#@comp:PWM1/SLICE_6">PWM1/SLICE_6</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         6     1.087<A href="#@net:PWMOutP4_c:R12C25B.Q1:68.PADDO:1.087">     R12C25B.Q1 to 68.PADDO      </A> <A href="#@net:PWMOutP4_c">PWMOutP4_c</A>
DOPAD_DEL   ---     1.084       68.PADDO to         68.PAD <A href="#@comp:PWMOutP3">PWMOutP3</A>
                  --------
                    2.304   (52.8% logic, 47.2% route), 2 logic levels.


Passed:  The following path meets requirements by 3.495ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:PWM1/SLICE_6">PWM1/PWMOut_15</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    Port       Pad            <A href="#@comp:PWMOutP4">PWMOutP4</A>

   Data Path Delay:     2.304ns  (52.8% logic, 47.2% route), 2 logic levels.

   Clock Path Delay:    1.191ns  (0.0% logic, 100.0% route), 0 logic levels.

 Constraint Details:
      1.191ns delay OSCH_inst to PWM1/SLICE_6 and
      2.304ns delay PWM1/SLICE_6 to PWMOutP4 (totaling 3.495ns) meets
      0.000ns hold offset OSCH_inst to PWMOutP4 by 3.495ns

 Physical Path Details:

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:ROUTE, 1.191,OSC.OSC,R12C25B.CLK,osc_clk">Clock path</A> OSCH_inst to PWM1/SLICE_6:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.191<A href="#@net:osc_clk:OSC.OSC:R12C25B.CLK:1.191">        OSC.OSC to R12C25B.CLK   </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.191   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:REG_DEL, 0.133,R12C25B.CLK,R12C25B.Q1,PWM1/SLICE_6:ROUTE, 1.087,R12C25B.Q1,69.PADDO,PWMOutP4_c:DOPAD_DEL, 1.084,69.PADDO,69.PAD,PWMOutP4">Data path</A> PWM1/SLICE_6 to PWMOutP4:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R12C25B.CLK to     R12C25B.Q1 <A href="#@comp:PWM1/SLICE_6">PWM1/SLICE_6</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         6     1.087<A href="#@net:PWMOutP4_c:R12C25B.Q1:69.PADDO:1.087">     R12C25B.Q1 to 69.PADDO      </A> <A href="#@net:PWMOutP4_c">PWMOutP4_c</A>
DOPAD_DEL   ---     1.084       69.PADDO to         69.PAD <A href="#@comp:PWMOutP4">PWMOutP4</A>
                  --------
                    2.304   (52.8% logic, 47.2% route), 2 logic levels.


Passed:  The following path meets requirements by 3.510ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:PWM1/SLICE_6">PWM1/PWMOut_15</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    Port       Pad            <A href="#@comp:PWMOutN3">PWMOutN3</A>

   Data Path Delay:     2.319ns  (56.8% logic, 43.2% route), 3 logic levels.

   Clock Path Delay:    1.191ns  (0.0% logic, 100.0% route), 0 logic levels.

 Constraint Details:
      1.191ns delay OSCH_inst to PWM1/SLICE_6 and
      2.319ns delay PWM1/SLICE_6 to PWMOutN3 (totaling 3.510ns) meets
      0.000ns hold offset OSCH_inst to PWMOutN3 by 3.510ns

 Physical Path Details:

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:ROUTE, 1.191,OSC.OSC,R12C25B.CLK,osc_clk">Clock path</A> OSCH_inst to PWM1/SLICE_6:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.191<A href="#@net:osc_clk:OSC.OSC:R12C25B.CLK:1.191">        OSC.OSC to R12C25B.CLK   </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.191   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:REG_DEL, 0.133,R12C25B.CLK,R12C25B.Q1,PWM1/SLICE_6:ROUTE, 0.818,R12C25B.Q1,R25C38B.C0,PWMOutP4_c:CTOF_DEL, 0.101,R25C38B.C0,R25C38B.F0,SLICE_2495:ROUTE, 0.183,R25C38B.F0,70.PADDO,PWMOutN4_c:DOPAD_DEL, 1.084,70.PADDO,70.PAD,PWMOutN3">Data path</A> PWM1/SLICE_6 to PWMOutN3:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R12C25B.CLK to     R12C25B.Q1 <A href="#@comp:PWM1/SLICE_6">PWM1/SLICE_6</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         6     0.818<A href="#@net:PWMOutP4_c:R12C25B.Q1:R25C38B.C0:0.818">     R12C25B.Q1 to R25C38B.C0    </A> <A href="#@net:PWMOutP4_c">PWMOutP4_c</A>
CTOF_DEL    ---     0.101     R25C38B.C0 to     R25C38B.F0 <A href="#@comp:SLICE_2495">SLICE_2495</A>
ROUTE         4     0.183<A href="#@net:PWMOutN4_c:R25C38B.F0:70.PADDO:0.183">     R25C38B.F0 to 70.PADDO      </A> <A href="#@net:PWMOutN4_c">PWMOutN4_c</A>
DOPAD_DEL   ---     1.084       70.PADDO to         70.PAD <A href="#@comp:PWMOutN3">PWMOutN3</A>
                  --------
                    2.319   (56.8% logic, 43.2% route), 3 logic levels.


Passed:  The following path meets requirements by 3.510ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              <A href="#@comp:PWM1/SLICE_6">PWM1/PWMOut_15</A>  (from <A href="#@net:osc_clk">osc_clk</A> +)
   Destination:    Port       Pad            <A href="#@comp:PWMOutN4">PWMOutN4</A>

   Data Path Delay:     2.319ns  (56.8% logic, 43.2% route), 3 logic levels.

   Clock Path Delay:    1.191ns  (0.0% logic, 100.0% route), 0 logic levels.

 Constraint Details:
      1.191ns delay OSCH_inst to PWM1/SLICE_6 and
      2.319ns delay PWM1/SLICE_6 to PWMOutN4 (totaling 3.510ns) meets
      0.000ns hold offset OSCH_inst to PWMOutN4 by 3.510ns

 Physical Path Details:

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:ROUTE, 1.191,OSC.OSC,R12C25B.CLK,osc_clk">Clock path</A> OSCH_inst to PWM1/SLICE_6:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       999     1.191<A href="#@net:osc_clk:OSC.OSC:R12C25B.CLK:1.191">        OSC.OSC to R12C25B.CLK   </A> <A href="#@net:osc_clk">osc_clk</A>
                  --------
                    1.191   (0.0% logic, 100.0% route), 0 logic levels.

      <A href="#@path:CLOCK_TO_OUT ALLPORTS 20.000000 ns CLKNET 'osc_clk' ;:REG_DEL, 0.133,R12C25B.CLK,R12C25B.Q1,PWM1/SLICE_6:ROUTE, 0.818,R12C25B.Q1,R25C38B.C0,PWMOutP4_c:CTOF_DEL, 0.101,R25C38B.C0,R25C38B.F0,SLICE_2495:ROUTE, 0.183,R25C38B.F0,71.PADDO,PWMOutN4_c:DOPAD_DEL, 1.084,71.PADDO,71.PAD,PWMOutN4">Data path</A> PWM1/SLICE_6 to PWMOutN4:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R12C25B.CLK to     R12C25B.Q1 <A href="#@comp:PWM1/SLICE_6">PWM1/SLICE_6</A> (from <A href="#@net:osc_clk">osc_clk</A>)
ROUTE         6     0.818<A href="#@net:PWMOutP4_c:R12C25B.Q1:R25C38B.C0:0.818">     R12C25B.Q1 to R25C38B.C0    </A> <A href="#@net:PWMOutP4_c">PWMOutP4_c</A>
CTOF_DEL    ---     0.101     R25C38B.C0 to     R25C38B.F0 <A href="#@comp:SLICE_2495">SLICE_2495</A>
ROUTE         4     0.183<A href="#@net:PWMOutN4_c:R25C38B.F0:71.PADDO:0.183">     R25C38B.F0 to 71.PADDO      </A> <A href="#@net:PWMOutN4_c">PWMOutN4_c</A>
DOPAD_DEL   ---     1.084       71.PADDO to         71.PAD <A href="#@comp:PWMOutN4">PWMOutN4</A>
                  --------
                    2.319   (56.8% logic, 43.2% route), 3 logic levels.

Report:    2.857ns is the maximum offset for this preference.

<A name="Report Summary"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "osc_clk" 88.670000 MHz ; |     0.000 ns|     0.303 ns|   1  
                                        |             |             |
CLOCK_TO_OUT ALLPORTS 20.000000 ns      |             |             |
CLKNET "osc_clk" ;                      |     0.000 ns|     2.857 ns|   2  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


<A name="Clock Domains Analysis"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------

Found 3 clocks:

Clock Domain: <A href="#@net:uart_rx1/UartClk[2]">uart_rx1/UartClk[2]</A>   Source: uart_rx1/SLICE_12.Q1   Loads: 29
   No transfer within this clock domain is found

Clock Domain: <A href="#@net:osc_clk">osc_clk</A>   Source: OSCH_inst.OSC   Loads: 1369
   Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ;

   Data transfers from:
   Clock Domain: <A href="#@net:uart_rx1/UartClk[2]">uart_rx1/UartClk[2]</A>   Source: uart_rx1/SLICE_12.Q1
      Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ;   Transfers: 9

   Clock Domain: <A href="#@net:CIC1_out_clkSin">CIC1_out_clkSin</A>   Source: CIC1Sin/SLICE_2199.Q0
      Covered under: FREQUENCY NET "osc_clk" 88.670000 MHz ;   Transfers: 10

Clock Domain: <A href="#@net:CIC1_out_clkSin">CIC1_out_clkSin</A>   Source: CIC1Sin/SLICE_2199.Q0   Loads: 153
   No transfer within this clock domain is found


Timing summary (Hold):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 1466856 paths, 1 nets, and 16495 connections (99.99% coverage)



Timing summary (Setup and Hold):
---------------

Timing errors: 10 (setup), 0 (hold)
Score: 37626 (setup), 0 (hold)
Cumulative negative slack: 37626 (37626+0)
